This project aims to significantly improve the performance of our DPDK-based Traffic Engine.

We target integrating multiqueue support and implementing architectural changes for optimized resource allocation. Transitioning to a new chiplet CPU architecture, we fine-tune traffic processing with efficient TX and RX computation, unlocking superior memory utilization. To further elevate functionality, we refine the API with an additional abstraction layer and introduce benchmarks to precisely measure API call performance.

Join us on the forefront of network innovation, where superior performance and functionality converge seamlessly for a transformative networking testing experience.

IxNetwork VE, layer 2/3 testing of virtual network infrastructure and devices.

What you will gain: Will dive deep into: • researching and implementing (Smart) NIC features that can be used for offloading of some data computing • researching and implementing new generation of Intel and AMD CPUs (chiplet architecture) and adapt our traffic engine into squeezing the most of these CPUs • automate and plot performance numbers from each new build. Provide reports to development and stakeholders on the progress of performance improvements over time.