Job Description • Responsible with semi-custom synthesis and STA for products developed in MCU16 division. • In charge with execution of synthesis, scan insertion and STA steps, according to the Microchip design flow and using sign-off regulations as provided by the flow experts. • Interfaces to top-level and module owners for taking over successive RTL releases, and performs top-level synthesis (Synopsys DC flow) ensuring timing closure and flow compliance. • Interfaces to Physical Design Engineer (who is in charge with digital P&R + layout), delivering post-synthesis netlist and also taking over post-layout netlist delivery for STA. • Performs STA using PrimeTime based on, and ensuring compliance to the latest sign-off regulations, computing ECO solutions as required (both for timing and functional fixes, as needed), as well as post-ECO STA updates. • Has in-depth knowledge of timing theory and details, with an emphasis on analog/digital interfaces, hard-macro functionality and connected topics.
Job Requirements • 4th year student in Electronics and Telecommunication, Automatics or Electrical Faculty • Basic knowledge of digital design and integrated circuits fundamentals. • Synopsis/Mentor/Cadence tools experience is a plus. • Good knowledge of English and good communications skills • Willingness to learn and keep up to date with latest flow definitions and design methodologies. • Ability to interface with required functions and people in a multi-site, multi-national environment.
The internship start date will be established together with the candidate.